Static Timing Analysis
We built Boson, a static timing analysis engine that achieves 700x run time improvements over legacy timing analysis tools.
Boson runs on
- a 100k gate netlist in 400 milliseconds
- a 1M gate netlist in 1 second
- a 7M gate netlist in 3 seconds
Try Boson
Boson is currently in beta. Contact us to get early access.
FAQ
- What is Boson?
- Boson is a static timing analysis engine that achieves 700x run time improvements over legacy timing analysis tools.
- How do I use Boson?
- Email us at contact@partcl.com to get early access.
- I am an academic. Can I use Boson?
- Yes, we offer a heavily discounted tier for academics. Email us at contact@partcl.com
- What benchmarks did you use?
- Our published benchmarks use an open source RISC-V core picorv32 and partitions of nvdla (a and c).
- What process nodes do you support?
- We support 7nm and above with more advanced nodes coming soon.
- What's next?
- We are currently working on an integrated placement and resizing tool for rapid optimization.
- What's the goal of Partcl?
- We want chip designers to benefit from the AI revolution. We enable this with fast, GPU accelerated EDA tools and models trained to efficiently sample the design space.
About
Will and Vamshi founded Partcl in 2024 after many sleepless nights wrestling with legacy tools in the final stretch before tapeout deadlines. With backgrounds from Cornell, UC Berkeley, and Stanford, and experience at Amazon, Apple, Nvidia, and multiple startups, they set out to build a better solution. Backed by Y Combinator, the world’s top early-stage investors, Partcl is redefining the future of chip design.